Modern communications systems are generally required to transmit data at both high rates and with little error. To satisfy such requirements, many communications systems employ error-control code to enhance system performance. Convolutional codes are a popular choice as codes used for error correction, due to both their capacity and reasonable coding simplicity. For example, convolutional codes are regularly used in various digital communications standards, such as DVB-T (Digital Video Broadcast-Terrestrial), which requires an average bit error rate (BER) of 2×10−4 for quasi error-free (QEF) operation. ISDB-T (Integrated Service Digital Broadcasting-Terrestrial) is another standard that also employs convolutional codes and may require a similar BER for regular operation. One subclass of convolutional codes used by various standards is the class including tail-biting codes. Several standards, such as HD-radio and LTE use such codes, as the last information bits are used as initial states of the encoder. However, each standard usually requires specific requirements for decoding and require extensive modification when switching between standards that use different formats of convolutional codes.
A current trend in consumer and communication service provider products is an integration of different communications standards within a single device. For example, a single device may require support for multiple standards that enable mobile broadcasts, wireless networking, and cellular networking. However, for each of the available standards, the parameters that defined such standards may be different, resulting in different design requirements for a Viterbi decoder.
Some existing solutions use software Viterbi decoders that may adapt to approximate dedicated hardware versions. However, such software solutions generally have a limited bandwidth (i.e., only up to a few Mbps). When Viterbi hardware is used, designers have been forced to install separate decoders for each standard. The drawbacks associated with this solution are that it requires a large amount of silicon area on any chip and that single-standard hardware Viterbi decoders may not later be used to support future standards.
In view of the foregoing, it would be desirable to improve support for multiple standards in Viterbi decoders. In particular, it would be desirable to construct hardware Viterbi decoders capable of handling a range of parameters associated with different standards.